Pmp/extracted pmp master #2528

OlivierBetschi · 2024-10-04T11:41:33Z

Extraction of the PMP outside of the MMU. Replacement of PR2476

github-actions · 2024-10-04T11:42:29Z

core/load_store_unit.sv

+    assign mmu_exception = pmp_exception;
+    assign icache_areq_o = pmp_icache_areq_o;
+    assign translation_valid = pmp_translation_valid;
+    assign mmu_paddr = pmp_paddr;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign mmu_exception = pmp_exception;

assign icache_areq_o = pmp_icache_areq_o;

assign translation_valid = pmp_translation_valid;

assign mmu_paddr = pmp_paddr;

assign mmu_exception = pmp_exception;

assign icache_areq_o = pmp_icache_areq_o;

assign translation_valid = pmp_translation_valid;

assign mmu_paddr = pmp_paddr;

github-actions · 2024-10-04T11:42:29Z

core/load_store_unit.sv

+        .CVA6Cfg      (CVA6Cfg),
+        .icache_areq_t(icache_areq_t),
+        .icache_arsp_t(icache_arsp_t),
+        .exception_t  (exception_t)
+    ) i_pmp_data_if (
+        .clk_i                 (clk_i),
+        .rst_ni                (rst_ni),
+        .enable_translation_i  (enable_translation_i),
+        .enable_g_translation_i(enable_g_translation_i),
+        .en_ld_st_translation_i(en_ld_st_translation_i),
+        .en_ld_st_g_translation_i(en_ld_st_g_translation_i),
+        .icache_areq_i         (icache_areq_i),
+        .icache_areq_o         (pmp_icache_areq_o),
+        .misaligned_ex_i       (misaligned_exception),
+        .lsu_req_i             (translation_req),
+        .lsu_vaddr_i           (mmu_vaddr),
+        .lsu_tinst_i(mmu_tinst),
+        .lsu_is_store_i        (st_translation_req),
+        .lsu_valid_o           (pmp_translation_valid),
+        .lsu_paddr_o           (pmp_paddr),
+        .lsu_exception_o       (pmp_exception),
+        .priv_lvl_i            (priv_lvl_i),
+        .v_i                   (v_i),
+        .ld_st_priv_lvl_i      (ld_st_priv_lvl_i),
+        .ld_st_v_i             (ld_st_v_i),
+        .pmpcfg_i              (pmpcfg_i),
+        .pmpaddr_i             (pmpaddr_i),
+        .data_allow_o          (pmp_data_allow),
+        .instr_allow_o         (pmp_instr_allow),
+        .match_any_execute_region_o (match_any_execute_region),
+        .misaligned_ex_o       (pmp_misaligned_ex)
+    );


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.CVA6Cfg (CVA6Cfg),

.icache_areq_t(icache_areq_t),

.icache_arsp_t(icache_arsp_t),

.exception_t (exception_t)

) i_pmp_data_if (

.clk_i (clk_i),

.rst_ni (rst_ni),

.enable_translation_i (enable_translation_i),

.enable_g_translation_i(enable_g_translation_i),

.en_ld_st_translation_i(en_ld_st_translation_i),

.en_ld_st_g_translation_i(en_ld_st_g_translation_i),

.icache_areq_i (icache_areq_i),

.icache_areq_o (pmp_icache_areq_o),

.misaligned_ex_i (misaligned_exception),

.lsu_req_i (translation_req),

.lsu_vaddr_i (mmu_vaddr),

.lsu_tinst_i(mmu_tinst),

.lsu_is_store_i (st_translation_req),

.lsu_valid_o (pmp_translation_valid),

.lsu_paddr_o (pmp_paddr),

.lsu_exception_o (pmp_exception),

.priv_lvl_i (priv_lvl_i),

.v_i (v_i),

.ld_st_priv_lvl_i (ld_st_priv_lvl_i),

.ld_st_v_i (ld_st_v_i),

.pmpcfg_i (pmpcfg_i),

.pmpaddr_i (pmpaddr_i),

.data_allow_o (pmp_data_allow),

.instr_allow_o (pmp_instr_allow),

.match_any_execute_region_o (match_any_execute_region),

.misaligned_ex_o (pmp_misaligned_ex)

);

.CVA6Cfg (CVA6Cfg),

.icache_areq_t(icache_areq_t),

.icache_arsp_t(icache_arsp_t),

.exception_t (exception_t)

) i_pmp_data_if (

.clk_i (clk_i),

.rst_ni (rst_ni),

.enable_translation_i (enable_translation_i),

.enable_g_translation_i (enable_g_translation_i),

.en_ld_st_translation_i (en_ld_st_translation_i),

.en_ld_st_g_translation_i (en_ld_st_g_translation_i),

.icache_areq_i (icache_areq_i),

.icache_areq_o (pmp_icache_areq_o),

.misaligned_ex_i (misaligned_exception),

.lsu_req_i (translation_req),

.lsu_vaddr_i (mmu_vaddr),

.lsu_tinst_i (mmu_tinst),

.lsu_is_store_i (st_translation_req),

.lsu_valid_o (pmp_translation_valid),

.lsu_paddr_o (pmp_paddr),

.lsu_exception_o (pmp_exception),

.priv_lvl_i (priv_lvl_i),

.v_i (v_i),

.ld_st_priv_lvl_i (ld_st_priv_lvl_i),

.ld_st_v_i (ld_st_v_i),

.pmpcfg_i (pmpcfg_i),

.pmpaddr_i (pmpaddr_i),

.data_allow_o (pmp_data_allow),

.instr_allow_o (pmp_instr_allow),

.match_any_execute_region_o(match_any_execute_region),

.misaligned_ex_o (pmp_misaligned_ex)

);

github-actions · 2024-10-29T11:00:59Z

❌ failed run, report available here.

github-actions · 2024-11-18T12:22:39Z

❌ failed run, report available here.

…o avoid raise condition in simulation

github-actions · 2024-11-20T15:00:52Z

❌ failed run, report available here.

github-actions · 2024-11-20T16:21:44Z

❌ failed run, report available here.

…irtual address

github-actions · 2024-11-20T17:02:15Z

❌ failed run, report available here.

github-actions · 2024-11-21T15:08:15Z

❌ failed run, report available here.

valentinThomazic · 2024-11-21T16:36:52Z

.gitlab-ci.yml

@@ -132,7 +132,7 @@ build_tools:

 .simu_after_script: &simu_after_script
  - for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" -o -name "*.yaml" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done


Suggested change

- for i in $(find verif/sim/out*/[vq]*_sim -type f $ -name "*.csv" -o -name "*.iss" -o -name "*.yaml" $) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done

- for i in $(find verif/sim/out*/[vq]*_sim -type f $ -name "*.csv" -o -name "*.iss" -o -name "*.yaml" $) ; do head -20000 $i > artifacts/logs/$(basename $i).head ; done

valentinThomazic · 2024-11-27T13:57:00Z

Hey @OlivierBetschi , I saw there was an issue with the dashboard not showing your logfiles.
Here are the logfiles for the failing generated test:
output
tb log
dasm
(bonus) tandem report

yanicasa · 2024-11-27T15:31:34Z

Seems ok in principle! but the fail pattern needs to be fixed to validate this functionality as it challenges a lot the LSU exceptions

github-actions · 2024-12-03T10:10:46Z

❌ failed run, report available here.

github-actions · 2024-12-03T10:15:58Z

❌ failed run, report available here.

github-actions · 2024-12-03T10:30:39Z

❌ failed run, report available here.

github-actions · 2024-12-03T10:36:50Z

❌ failed run, report available here.

valentinThomazic · 2024-12-03T12:34:23Z

@OlivierBetschi I have manually rerun the smoke gen tests and it passed this time.
The asic synthesis fails because a patch needs update on our side.
Spyglass job also fails because the count of W123 : "A signal or variable has been read but is not set" increased from 11 to 12 on your commit.
I fixed the patch and will suggest the modifications to you

valentinThomazic · 2024-12-03T12:55:39Z

I am not able to propose changes since the file is not changed on your PR, here is a patch:

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 048e75324..16ed6ac36 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -275,7 +275,7 @@ asic-synthesis:
     - echo $DV_TARGET
     - source ./verif/sim/setup-env.sh
     - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
-    - git -C ${SYNTH_SCRIPT_PATH} checkout 1e166766d2c91ca905577cccc70813a2a8bbefc2
+    - git -C ${SYNTH_SCRIPT_PATH} checkout cce5ea41
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
@@ -546,7 +546,7 @@ simu-gate:
     - echo $PERIOD
     - source ./verif/sim/setup-env.sh
     - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
-    - git -C ${SYNTH_SCRIPT_PATH} checkout 1e166766d2c91ca905577cccc70813a2a8bbefc2
+    - git -C ${SYNTH_SCRIPT_PATH} checkout cce5ea41
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh

Please apply, commit and push it on your branch

OlivierBetschi · 2024-12-03T14:14:51Z

@valentinThomazic thanks, I added your patch for gitlab. I can fix the spyglass issue if you give me the message, as I do not see the spyglass reports in the provided logs

github-actions · 2024-12-03T14:15:44Z

❌ failed run, report available here.

valentinThomazic · 2024-12-03T14:25:56Z

@OlivierBetschi

W123 : Following Bits of signal 'pmp_paddr' (File Name: /gitlab-runner/runner_riscv-public/builds/yD5zmwgi3/0/riscv-ci/cva6/core/load_store_unit.sv Line No.: 356) are read but not set
	[33:12]

The asic synthesis is working, it is considered failed because the gate count is different than the expected one.

Everything should pass if you fix the spyglass error and update .gitlab-ci/expected_synth.yml to match the new gate count.

github-actions · 2024-12-03T15:26:06Z

❌ failed run, report available here.

OlivierBetschi · 2024-12-03T16:06:00Z

@valentinThomazic I updated the RTL. Hopefully the spyglass is cleaner now. But i get the unaligned load store failed again. How should we proceed ? do you think we merge regardless or do you want to fix #2645 to be sure ?

github-actions · 2024-12-03T17:16:30Z

❌ failed run, report available here.

valentinThomazic · 2024-12-03T17:29:33Z

@OlivierBetschi I ran another pipeline manually but there are issues that should be addressed first.
I will let @JeanRochCoulon decide if it is ok to merge or not when the PR is fixed

JeanRochCoulon · 2024-12-03T21:17:44Z

Synthesis is failed, gate simulation is failed: errors can be collected at the end of synthesis CI log

github-actions · 2024-12-04T08:57:53Z

✔️ successful run, report available here.

OlivierBetschi · 2024-12-04T09:01:41Z

@JeanRochCoulon the remaining issues in the CI are fixed. Thank you for your help @valentinThomazic

JeanRochCoulon · 2024-12-04T09:04:10Z

Great job @OlivierBetschi We can merge !

OlivierBetschi requested review from JeanRochCoulon and zarubaf as code owners October 4, 2024 11:41

github-actions bot reviewed Oct 4, 2024

View reviewed changes

CoralieAllioux and others added 15 commits November 19, 2024 11:34

First public version of extracted pmp

eff3a7f

Remove misaligned_ex computation: get it from outside

4517afd

Remove data and instr pmps, get match_execution from outside

90f3bae

Get data and instr allow from outside

0bc197d

Simplify fetch_instruction exception when instr not allow by pmp

04a54f7

Simplify exception when data not allow by pmp, getting it from outside

a4fbed0

Apply verible format

436d563

Integrate PMP fully outside MMU

2998bb7

fix translation_valid and dtlb_ppn when no mmu

405e02e

Add pmp_data_if in needed file lists

e85adcb

Fix exception tval when translation is enabled

ca97962

integrate no_locked assertions for pmp: now in blocking assignments t…

77ee14d

…o avoid raise condition in simulation

Fix mixed assignment for no_locked_if

1dc3f0a

Remove assertion no_locked from pmp: need clk and reset

1b635fa

Apply verible format

45d0176

OlivierBetschi requested a review from jquevremont as a code owner November 20, 2024 14:52

OlivierBetschi force-pushed the pmp/extracted_pmp_master branch from 568177b to e4cca2c Compare November 20, 2024 16:15

Use physical address from the MMU output as input to PMP instead of v…

f88bc36

…irtual address

OlivierBetschi force-pushed the pmp/extracted_pmp_master branch from e4cca2c to f88bc36 Compare November 20, 2024 16:54

Increase log file

dcba761

valentinThomazic reviewed Nov 21, 2024

View reviewed changes

OlivierBetschi added 4 commits December 3, 2024 10:25

Add 1 cycle delay for misaligned exception and valid translation

cff299f

Restore gitlab ci settings

61f31ba

Fix log file name

85bb2f1

Merge branch 'master' into pmp/extracted_pmp_master

ff70060

valentinThomazic mentioned this pull request Dec 3, 2024

[BUG] Result of riscv_unaligned_load_store_test is inconsistent #2645

Open

1 task

Patch commit for CI

3e7b452

OlivierBetschi added 2 commits December 3, 2024 16:17

Remove unused signal

14065ae

Update gate count to match addition on PMP

2ecc2c7

Fix dtlb_ppn assignment and remove some unused signals

e36852b

JeanRochCoulon merged commit 23355d2 into openhwgroup:master Dec 4, 2024
10 checks passed

OlivierBetschi mentioned this pull request Dec 4, 2024

[Pmp] Verif plan TXT #2457

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Pmp/extracted pmp master #2528

Pmp/extracted pmp master #2528

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JeanRochCoulon commented Dec 4, 2024

		@@ -132,7 +132,7 @@ build_tools:

		.simu_after_script: &simu_after_script
		- for i in $(find verif/sim/out/[vq]_sim -type f \( -name ".csv" -o -name ".iss" -o -name "*.yaml" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done

Pmp/extracted pmp master #2528

Pmp/extracted pmp master #2528

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